The present invention relates to a highly integrated semiconductor memory device and a method of manufacturing the same.
With the recent tendency toward high integration of semiconductor memory devices, semiconductor memory devices such as a DRAM have been miniaturized. With the miniaturization, a capacitor area responsible for storing charges tends to be reduced, leading to a reduction in capacitance. As the capacitance is reduced, reading performance by a sense amplifier is degraded and a capacitor storage electrode is negatively affected by electron-hole pairs generated by an .alpha. ray, with the result that memory data is destroyed. Such a so-called soft error has been arisen as a significant problem.
To prevent deterioration in reading performance, capacitance is tried to be increased. On the other hand, to increase a soft-error resistance, it is considered useful that a contact area of a diffusion layer in contact with a capacitor storage electrode is reduced to thereby decrease an efficiency in collecting .alpha. ray-induced charges.
To satisfy these requirements simultaneously, a stacked type semiconductor memory device has been proposed. The stacked type semiconductor memory device employs a stacked capacitor structure in place of a conventionally-used capacitor structure in which the diffusion layer itself is used as the capacitor storage electrode (storage node electrode). The stacked capacitor is formed of a capacitor storage electrode stacked on a semiconductor substrate. To ensure the capacitor area, a COB (capacitor over bit-line) structure has been employed in practice in DRAMs of 16M bit generation. In the COB structure, a capacitor is formed over the bit line layer.
The semiconductor memory device of a stacked type cell structure having the capacitor storage electrode formed on the bit line is disclosed in, for instance, "Highly Manufacturable Process Technology for Reliable 256M bit and 1 G bit DRAMs", H. K. Kang et al. IEDM Technical Digest p635 (1994).
Hereinbelow, the present invention will be explained with reference to FIG. 1. Reference symbol MC represents a memory cell region and reference symbol PC represents a peripheral circuit region in FIG. 1.
A conventionally-used DRAM having a stacked capacitor of a COB structure has an element isolating region 102, which is formed in the memory cell region on a semiconductor substrate 101, and an active region which is sandwiched by the element isolating regions 102. The active region of the DRAM includes a gate electrode (word line) 104a and first conductivity type source/drain regions 105a. The gate electrode 104a is formed in a predetermined position on a main surface of the semiconductor substrate 101, via a gate insulating film 103. The first conductivity type source/drain regions 105a are formed on a predetermined region of a second conductivity type in the main surface of the semiconductor substrate 101.
Furthermore, the DRAM has a passing word line (gate electrode) 104b which is formed on the element isolating region 102, a gate electrode (word line) 104a, an insulating film 106 which covers the passing word line 104b, a capacitor storage electrode (storage node electrode) 113 which is connected to one of the source/drain regions 105a close to the gate electrode (word line) 104a via a buried electrode 107, and a bit line 110a which is connected to the other one of the source/drain regions 105a via the buried electrode 107.
Furthermore, the DRAM has capacitor upper electrodes (cell plate) 115a and 115b (which are formed as the same layer), and a conducting layer (first wiring layer) 123b which is present in the peripheral circuit region. The capacitor upper electrodes 115a and 115b are formed on the capacitor storage electrode (storage node electrode) 113 with a capacitor dielectric film 114 interposed therebetween. The conducting layer (first wiring layer) 123b is connected to the capacitor upper electrode (cell plate) 115b by way of a buried electrode 120 with an interlayer insulating film 116 interposed between them.
In this case, a transistor TR is formed of the gate insulating film 103, the gate electrode (word line) 104a and the source/drain regions 105a. In the DRAM having a stacked capacitor of the COB structure, the bit line 110a is formed underneath the capacitor storage electrode (Storage node electrode) 113, as shown in FIG. 1.
Now, a conventionally-employed method of manufacturing the semiconductor memory device of this type will be explained below. Since a feature of the present invention resides in the steps after formation of the capacitor upper electrodes (cell plates) 115a, 115b, there will be briefly explained the steps before the step of forming capacitor upper electrodes (cell plates) 115a, 115b, referring to conventionally-employed steps shown in FIGS. 2-7.
As shown in FIG. 2, the element isolating region 102 is first formed by LOCOS (Local Oxidation of Silicon) on a main surface of a p-type semiconductor substrate 101 within the memory cell region. Second, as shown in FIG. 3, a gate oxide film 103, gate electrodes (word lines) 104a, 104b, N-type source/drain regions 105a, and an insulating film 106 covering the gate electrodes (word lines) 104a, 104b, are sequentially formed. Subsequently, a buried electrode 107 is formed in a self-alignment manner with the insulating film 106 by depositing the conductive film.
Then, an interlayer insulating film 108 is formed over the entire surface. A contact hole 109a is formed in the interlayer insulating film 108. Thereafter, a bit line 110a is formed of tungsten (W) over an entire surface including an inner surface of the contact hole 109a.
As shown in FIG. 4, an interlayer insulating film 111 is formed over the entire surface. A contact hole 112 is formed extending through the interlayer film 111 and the interlayer film 108. Subsequently, a capacitor storage electrode (storage node electrode) 113, a capacitor dielectric film 114, and a capacitor upper electrodes (cell plates) 115a, 115b are successively formed.
As shown in FIG. 5, an interlayer insulating film 116 is deposited over the entire surface of the substrate. The surface of the interlayer insulating film 116 is polished flat by CMP (Chemical Mechanical Polishing).
To permit the capacitor upper electrodes (cell plates) 115a, 115b to electrically connect to the outside, a contact hole 117 is formed by RIE (Reactive Ion Etching). Subsequently, a barrier metal layer 118 (a Ti/TiN stacked film) and a conductive film 119 (tungsten, W) are deposited inside the contact hole 117 and on the interlayer insulating film 116. CMP is applied using the interlayer insulating film 116 as a stopper. As a result, a buried electrode 120 is formed.
As shown in FIG. 6, conducting layers (wiring layers) 123a, 123b are formed of a barrier metal layer 121 and a conducting layer 122 (aluminium, etc). Then, an interlayer insulating film 124 is deposited as shown in FIG. 7. A contact hole 125 is formed at a desired position. Furthermore, a barrier metal layer 126 and a conducting layer 127 (aluminium etc.) are deposited to form a conducting layer (wiring layer) 128. Subsequently, a protection film 129 (not shown) is formed, on which an opening of a pad electrode portion is further formed. In this manner, the semiconductor memory device is accomplished. Note that the contact hole on the upper electrode is formed by anisotropic etching, namely, RIE.
As described, in the conventionally-employed semiconductor memory device and the manufacturing method thereof, a plurality of contact holes different in depth, such as the contact hole 117 between the conducting layer (first wiring layer) 123b and the capacitor upper electrode (cell plate) 115b, and a contact hole (not shown) between the same layer as the conducting layer 123b (first wiring layer) and the same layer as the bit line 110a, are formed simultaneously in the same method. It follows that the contact hole shallow in depth inevitably receives impact by accelerated ions even after a desired over-etching is applied thereto. The impact lasts until a desired over-etching to the most deepest contact hole is completed.
During the contact hole formation step, the capacitor upper electrodes (cell plates) 115a, 115b are electrically floated. Therefore, charges tend to be accumulated. The impact of the accelerated ions changes electric potential of one of electrodes of the capacitor, generating a potential difference between the capacitor upper electrodes (cell plates) 115a, 115b and the capacitor storage electrode (storage node electrode) 113. As a result, the capacitor dielectric film 114 is damaged by electrostatic breakage etc.